Conventionally, testing of integrated circuits involves placing the microchip under test on a device under test (“DUT”) card connected to a tester. The tester is used to test the integrated circuit for functionality. In instances where the tester is sufficiently fast, the integrated circuit may be tested at a maximum frequency of operation.
Integrated circuits which are more or less standard products are often speed binned. Examples of such standard products include memories, processors and programmable logic devices, among others. One form of programmable logic device which is a standard product is a Field Programmable Gate Array (“FPGA”).
Speed binning an integrated circuit involves testing to determine a frequency, such as the maximum frequency of operation of the integrated circuit, for which it continues to function correctly. Accordingly, some integrated circuits will operate at faster speeds than other same or similarly manufactured integrated circuits whether from same or different production lots. Conventionally, speed binning is used to identify parts that can operate at frequencies in excess of a baseline frequency for sale at a premium price.
Additionally, integrated circuits are tested for functionality. A host integrated circuit with an embedded processor block may include an embedded processor and interface circuitry for interfacing the embedded processor with circuitry of the host integrated circuit. This interface circuitry may operate at the same frequency of operation as the embedded processor. Examples of such interface circuitry include on-Chip Memory (OCM) controllers as found in the Virtex-II Pro FPGA from Xilinx Corp. of San Jose, Calif. To test such interface circuitry for functionality, such interface circuitry should be run at the frequency of operation of the embedded processor.
However, testers have certain limitations. For example, testers have problems testing integrated circuits having an embedded processor block with a frequency of operation significantly faster than a host integrated circuit in which the embedded processor block is embedded. Another limitation of testers is being able to control, from externally accessible pins of the host integrated circuit, internal pins of the embedded processor block, especially when such internal pins significantly out number the externally accessible pins. Limitations of access to internal pins impedes functional testing of an embedded processor block, including testing interface circuitry thereof.
Accordingly, it would be desirable and useful to provide a better means for performance testing, including speed and functional testing, an embedded processor block in an integrated circuit device.